小跑蛇

1，使用VHDL (或者Verilog HDL) 编写两个译码器，分别控制8个数码管的片选和位选；
片选
使用hexto7seg进行数码管的片选。

image.png

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE ieee.std_logic_arith.all;

ENTITY hextocs IS
  PORT (
        inp : IN Std_Logic_Vector (4 DOWNTO 0);
        output : OUT Std_Logic_Vector (2 DOWNTO 0));
END hextocs;

ARCHITECTURE arc OF hextocs IS
BEGIN
   process(inp)
   begin
      CASE inp IS
          WHEN "00000" => output <= "000";
          WHEN "00001" => output <= "001";
          WHEN "00010" => output <= "010";
          WHEN "00011" => output <= "011";     
          WHEN "00100" => output <= "100";
          WHEN "00101" => output <= "101";
          WHEN "00110" => output <= "110";
          WHEN "00111" => output <= "111";
          WHEN "01000" => output <= "111";
          WHEN "01001" => output <= "111";
          WHEN "01010" => output <= "111";
          WHEN "01011" => output <= "110";
          WHEN "01100" => output <= "101";
          WHEN "01101" => output <= "100";
          WHEN "01110" => output <= "011";
          WHEN "01111" => output <= "010";
          WHEN "10000" => output <= "001";
          WHEN "10001" => output <= "000";
          WHEN "10010" => output <= "000";
          WHEN "10011" => output <= "000";
          WHEN OTHERS => output <= "000";
      END CASE;
  end process;
END arc;

位选
使用hexto7seg控制数码管的abcdefg7段。

image.png

LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE ieee.std_logic_arith.all;

ENTITY hexto7seg IS
  PORT (
        inp : IN Std_Logic_Vector (4 DOWNTO 0);
        output : OUT Std_Logic_Vector (6 DOWNTO 0));
END hexto7seg;

ARCHITECTURE arc OF hexto7seg IS
BEGIN
   process(inp)
   begin
      CASE inp IS
          WHEN "00000" => output <= "0000001";
          WHEN "00001" => output <= "0000001";
          WHEN "00010" => output <= "0000001";
          WHEN "00011" => output <= "0000001";     
          WHEN "00100" => output <= "0000001";
          WHEN "00101" => output <= "0000001";
          WHEN "00110" => output <= "0000001";
          WHEN "00111" => output <= "0000001";
          WHEN "01000" => output <= "0000010";
          WHEN "01001" => output <= "0000100";
          WHEN "01010" => output <= "0001000";
          WHEN "01011" => output <= "0001000";
          WHEN "01100" => output <= "0001000";
          WHEN "01101" => output <= "0001000";
          WHEN "01110" => output <= "0001000";
          WHEN "01111" => output <= "0001000";
          WHEN "10000" => output <= "0001000";
          WHEN "10001" => output <= "0001000";
          WHEN "10010" => output <= "0010000";
          WHEN "10011" => output <= "0100000";
          WHEN OTHERS => output  <= "0000000";
      END CASE;
  end process;
END arc;

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2，使用计数器宏模块产生加法计数，作为两个译码器的输入，模值取决于循环状态的个数，本例共取20个状态。

image.png

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3，两点注意
使能数码管模块

image.png image.png

要对系统时钟分频
太快的刷新速度会导致数码管显示异常。

image.png

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4，效果演示
https://www.bilibili.com/video/BV1E24y1f766/